1. Field of Invention
The present invention relates to an image processing apparatus and method having compression/decompression function for image data, and more particularly to an image processing apparatus and method for high-performance and real time conversion of image data by the JBIG (Joint Bi-level Image Experts Group) standard utilizing the ping-pong buffer and line buffer to generate necessary context.
2. Description of Related Arts
Please refer to the prior art described in U.S. Pub. No. 20020024525. As shown in FIG. 1 of U.S. Pub. No. 20020024525, it illustrates a hardware block diagram of a typical sequential JBIG process. Referring to FIG. 1, reference numerals 101 to 104 denote line buffers which sequentially update and store image data for one line in synchronism with clocks (not shown), thus outputting image data for four lines including a line to be encoded and reference lines for template generation to a TP discriminator 105 and adaptive arithmetic encoder 107.
Image data input from an input terminal 100 at a rate of one pixel/clock in synchronism with transfer clocks (not shown) is stored in the line buffer 101. The line buffer 101 stores the data, and simultaneously reads out image data for the previous line and outputs it to the line buffer 102 in synchronism with the transfer clocks. The line buffer 102 stores the data output from the line buffer 101 in synchronism with the transfer clocks, and simultaneously reads out the stored data for the previous line and outputs it to the line buffer 103, as in the line buffer 101. In this manner, data are sequentially transferred to the line buffers 102, 103, and 104 while being updated, thus simultaneously extracting delayed data for four lines from the memories. In this example, the data read out from the line buffer 102 corresponds to the line to be encoded.
Reference numeral 105 denotes a TP (typical prediction) discriminator for comparing data read out from the line buffer 101 and data of the immediately above line read out from the line buffer 102 for one line so as to check if data for one line, which is read out from the line buffer 101 and is stored in the line buffer 102, allows typical prediction. A discrimination result indicating whether data allows typical prediction (LNTPy=0) or not (LNTPy=1) is output to a register 106 every time a process for one line is completed, and is held in the register to update the register value. Reference numeral 107 denotes an adaptive arithmetic encoder for receiving data for three lines, which are read out from the line buffers 102, 103, and 104, and generating template data corresponding to a pixel to be encoded using shift registers (not shown). The adaptive arithmetic encoder makes an adaptive arithmetic coding operation of the pixel to be encoded using this template data, thus generating and outputting encoded data. At the head of each line, a temporary pixel is computed using the register value held in the register 106, and an adaptive arithmetic coding operation is made using a fixed template therefor so as to encode the typical prediction result by adaptive arithmetic coding, thus generating and outputting encoded data.
However, since the prior art implements the TP (typical prediction) process by hardware, as shown in FIG. 1 of U.S. Pub. No. 20020024525, four line buffer memories for reference lines are required for the TP process, thus increasing the hardware scale. Furthermore, in the example shown in FIG. 1 of U.S. Pub. No. 20020024525, since all the line buffer memory update process, TP discrimination process, and adaptive arithmetic coding operation are parallelly executed in synchronism with identical clocks, each line to be encoded requires a processing time given by the number of pixels for one line.times.clocks although the TP process that can reduce the number of pixels to be encoded if they allow typical prediction and that can achieve high-speed processing is used.
Accordingly, according to the prior art described in U.S. Pub. No. 20020024525, there are at least one line buffer memory for processing TP, and three line buffer memories for processing context, wherein the TP memory and the context memory are sequentially assembled for later purposes. Therefore, there are at least four line buffers necessary for processing TP (typical predication) and combining the context, a rather larger memory will be required for accomplishing such tasks. Furthermore, when the high resolution image is processed, the SRAM will eaten up as octuple as much, that is to say, more SRAM would be occupied by such JBIG system. What is more, it is awesomely time-consuming for wait such TP (typical prediction), as well as the context are forwarded to the adaptive arithmetic encoder, which is intolerable for most of users.